[1]张超,刘峥,赵伟.一种染色体编码新方法的硬件进化[J].智能系统学报,2011,6(5):450-455.
ZHANG Chao,LIU Zheng,ZHAO Wei.Hardware evolution based on a new chromosome encoding method[J].CAAI Transactions on Intelligent Systems,2011,6(5):450-455.
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ZHANG Chao,LIU Zheng,ZHAO Wei.Hardware evolution based on a new chromosome encoding method[J].CAAI Transactions on Intelligent Systems,2011,6(5):450-455.
一种染色体编码新方法的硬件进化
《智能系统学报》[ISSN 1673-4785/CN 23-1538/TP] 卷:
6
期数:
2011年第5期
页码:
450-455
栏目:
学术论文—人工智能基础
出版日期:
2011-10-30
- Title:
- Hardware evolution based on a new chromosome encoding method
- 文章编号:
- 1673-4785(2011)05-0450-06
- 关键词:
- 硬件进化; 染色体编码; FPLA; Verilog硬件语言
- Keywords:
- hardware evolution; chromosome encoding; field programmable logic array(FPLA); Verilog HDL
- 分类号:
- TP18;TP302.8
- 文献标志码:
- A
- 摘要:
- 提出了基于FPLA的染色体编码及在此基础上的并行硬件进化方法.该编码方式以与或非门为基本单元，进化时将电路编码染色体按逻辑门分解，进行适应度计算时采用分解逆过程使染色体合并，可以有效缩短进化时间，有利于大规模复杂电路的进化.以4位二进制码转换为格雷码的电路为例进行试验，该方法在20次实验中平均速度提高了32.25%.为实现内进化编写了由染色体生成Verilog硬件语言的C程序，该编码方式同时适用于多输入多输出电路进化且染色体长度可变，利用此特性生成了异构电路，完成了容错，对于实现故障模块在线修复，提高太空恶劣环境中电子系统可靠性具有一定意义.
- Abstract:
- This paper proposed an FPLAbased chromosome encoding approach and a parallel hardware evolution method on the basis of a new encoding approach. The ANDORNOT gates are the basic units of the chromosome, so by decomposing the chromosome while evolving and integrating it when computing the adaptation, the evolution time can be shortened. This benefits the evolution of massive and complex circuits. Taking the circuit of changing 4 bits binary code to gray code as an example, the result shows that the average speed increases 32.25 percent over 20 evolutions when using the proposed method. In order to facilitate intrinsic evolutions, the C program was also exploited for translating the chromosome to Verilog hardware language. The encoding method was able to handle multiinput and multioutput circuit evolution, and the chromosome’s length was variable. According to the evolution of the heterogeneous circuits based on this feature, fault tolerance was achieved. This work is significant for online repair used to improve the reliability of electronic systems exposed to harsh space environments.
- 参考文献/References:
-
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［4］KALGANOVA T. Bidirectional incremental evolution in extrinsic evolvable hardware［C］//Proceedings of the Second NASA/DOD Workshop on Evolvable Hardware (EH’00). Washington, DC, USA: IEEE Computer Society, 2000: 6574.
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［6］Xilinx Inc. Two flows for partial reconfiguration: modulebased or difference based［EB/OL］. ［20100511］. http: //www. xilinx. com /support/documentation/application_notes/xapp290. pdf.
［7］原亮,丁国良,褚杰,等.EHW实现过程中VHDL程序自动生成研究［J］.军械工程学院学报, 2008, 20(4): 6669.
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［8］姚爱红，张国印，关琳.基于动态可重构FPGA的自演化硬件概述［J］.智能系统学报, 2008, 3(5): 436442.
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［9］姚睿,王友仁,于盛林，等.具有在线〖CM4*2/3-4〗修复能力的强容错三模冗余系统设计及实验研究［J］.电子学报, 2010, 38(1): 177183.
?YAO Rui, WANG Youren, YU Shenglin, et al. Design and experiments of enhanced faulttolerant triplemodule redundancy systems capable of online selfrepairing［J］. Acta Electronica Sinica, 2010, 38(1): 177183.
- 相似文献/References:
-
[1]姚爱红,张国印,关 琳.基于动态可重构FPGA的自演化硬件概述[J].智能系统学报,2008,3(5):436.
YAO Ai-hong,ZHANG Guo-yin,GUAN L in.A survey of dynam ically and partially reconf igurable FPGA-based self-evolvable hardware[J].CAAI Transactions on Intelligent Systems,2008,3():436.
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备注/Memo
收稿日期： 2010-12-20.
基金项目： 陕西省自然科学基础研究计划资助项目（SJ08F19）.
通信作者：张超.E-mail:gnszzc@163.com.
作者简介：
张超，男，1986年生，硕士研究生，主要研究方向为空间信号处理系统及其容错技术.
刘峥，男，1964年生，教授,博士生导师,西安电子科技大学雷达信号处理国家重点实验室副主任，主要研究方向为多源信息融合、雷达信号处理及精确制导技术.目前承担国家“863”计划重点项目、空军重大工程研发项目、国防科技预研项目等多项科研项目.
更新日期/Last Update:
2011-11-16