[1]LIU Peihua,LU Huaxiang,GONG Guoliang,et al.Design of an FPGAbased doubleprecision floatingpoint matrix multiplier with pipeline architecture[J].CAAI Transactions on Intelligent Systems,2012,7(4):302-306.
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Design of an FPGAbased doubleprecision floatingpoint matrix multiplier with pipeline architecture

CAAI Transactions on Intelligent Systems[ISSN 1673-4785/CN 23-1538/TP] Volume: 7 Number of periods: 2012 4 Page number: 302-306 Column: 学术论文—智能系统 Public date: 2012-08-25
Title:
Design of an FPGAbased doubleprecision floatingpoint matrix multiplier with pipeline architecture
Author(s):
LIU Peihua;  LU Huaxiang;  GONG Guoliang;  LIU Wenpeng
Lab of Artificial Neural Networks, Institute of Semiconductors, Chinese Academy of Science, Beijing 100083, China
Keywords:
matrix multiplication;  FPGA;  loop pipeline;  Cslow retiming;  multiplia design
CLC:
TP332.2
DOI:
-
Abstract:
Many application areas, such as digital communication and image processing, make extensive use of matrix multiplication operations, and the computational performance of this operation is critical for the whole system. A parallel doubleprecision floatingpoint matrix multiplier with pipeline architecture was designed to improve the computational performance. The design was implemented in a Xilinx Virtex5 LX155 field programmable gate array (FPGA). Up to 10 processing elements were integrated in a single FPGA device, and they were arranged as an array to achieve parallel computation. The processing elements employed pipelined architecture to increase the speed, and Cslow retiming was applied to solve the datarelated conflicts issues on the loop pipeline. The postRoute simulation results show that the peak performance of the matrix multiplier can achieve 5 000 MFLOPS. In addition, the matrix multiplication experiments with different dimensions were carried out, and the results confirm that the design achieved high computational performance.
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Last Update: 2012-09-26

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